VLSI - Physical Design Training Batch Starting on May 6, 2019; Entrance exam on March 23, 2019

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Faculty

  • Teacher Name : Mr. Srinivasa Rao Kakumanu(KS)
  • experience : 23+ years
  • educational qualification : B.Tech from OU
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KS is CEO of Institute of Silicon Systems. He has been in VLSI industry for the last 19 years and he worked as General Manager, ASIC Design (India), Infotech Enterprises Ltd until end of last year. Mr. KS lead/managed 70+ ASICs all the way from 0.14um to 40nm – working at QualCore, TTM (and later Infotech - Infotech acquired TTM in Sept, 2008) and Ikanos. He was in the US between 2000-2007, managed teams at TTM inc., and Ikanos. Mr. KS quit Infotech in Nov, 2010 and he has been training students at Institute of Silicon Systems Private Ltd in Madhapur, Hyderabad since then.

  • Teacher Name : Mrs. Sarala Beeneedi
  • experience : 30+ years
  • educational qualification : M.Tech from JNTU
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Sarala Beeneedi is Technical Director of Institute of Silicon Systems. She has over 32 years of industry experience spanning FPGA (Xilinx FPGAs) design, ASIC design, Digital design and Hardware design. She was in USA from 2001 to 2005, worked for Physical Design services company (Time To Market Inc) as Senior ASIC Designer. She was Vice President of FPGA group at Taray Technologies India Pvt Ltd and made significant contribution for the growth of the company. She has extensive hands on experience and played key role for the last ten years being in managerial position.