Design Verification batch starting on 4th November 2019, entrance exam on October 20, 2019.      

Physical Design

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ISS COURSES

VLSI - Physical Design Training

Prerequisites:

B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics;

Admission Test Syllabus:

Need to qualify the screening test and technical interview.Test would be conducted in Basic Electronics - BJT, FET, CMOS; Digital Electronics - Number Systems, Boolean Algebra, K-Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits and Counters. (All are subjective type questions)

Course content:

Fundamental concepts in Digital abstraction, Static discipline, MOSFET switch, CMOS basics, Digital circuit speed, NMOS logic, CMOS logic, Combinational logic, Sequential logic, Synchronous sequential design, Timing awareness, Setup/Hold requirement significance, Asynchronous circuits, Metastability, Synchronization, Logic synthesis fundamentals, Advanced logic synthesis (PLE based), Floor planning, Power planning, Placement, Clock tree synthesis, Routing, Signal integrity, IR-drop analysis, OCV analysis, Static timing analysis and advanced Physical design concepts like Low power design techniques. The trainees get to work on 5 to 6 different designs. The assignments are designed in such a way that trainees have a clear understanding about handling the design from Synthesis to Sign-off within the given specification limits of Area, Timing and Power.

VLSI - Design Verification Training

Prerequisites:

B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics;

Admission Test Syllabus:

Need to qualify the screening test and technical interview.Test would be conducted in Basic Electronics - BJT, FET, CMOS; Digital Electronics - Number Systems, Boolean Algebra, K-Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits and Counters. (All are subjective type questions)

Course content:

Fundamental concepts in Digital abstraction, Static discipline, MOSFET switch, CMOS basics, Digital circuit speed, NMOS logic, CMOS logic, Combinational logic, Sequential logic, Synchronous sequential design, Timing awareness, Setup/Hold requirement significance, Asynchronous circuits, Metastability, Synchronization, Logic synthesis fundamentals, Advanced logic synthesis (PLE based), Floor planning, Power planning, Placement, Clock tree synthesis, Routing, Signal integrity, IR-drop analysis, OCV analysis, Static timing analysis and advanced Physical design concepts like Low power design techniques. The trainees get to work on 5 to 6 different designs. The assignments are designed in such a way that trainees have a clear understanding about handling the design from Synthesis to Sign-off within the given specification limits of Area, Timing and Power.

VLSI - Analog Layout Training

Prerequisites:

B.E/B.Tech in ECE/EEE, M.E/M.Tech/M.S in VLSI/Embedded Systems/Digital Electronics;

Admission Test Syllabus:

Need to qualify the screening test and technical interview.Test would be conducted in Basic Electronics - BJT, FET, CMOS; Digital Electronics - Number Systems, Boolean Algebra, K-Maps, Logic Gates, Logic Families, Combinational Circuits, Sequential Circuits and Counters. (All are subjective type questions)

Course content:

Fundamental concepts in MOSFET fundamentals, Second order effects, Digital logic gates, Fabrication concepts, Latch Up, Analog building blocks, Analog layout concepts like Module based floor plan techniques, Device Matching techniques, Routing techniques (Power, Signal), Shielding concepts, Deep sub-micron process challenges like Well proximity, LOD and STI effects, ESD concepts and Layout guidelines. Physical verification concepts like LVS, DRC and Antenna with Parasitic extraction. Exposure to the Importance of reliability checks like EMIR analysis, DFM checks and ESD path checks. The trainees get to work on 5 to 6 different designs. The assignments are designed in such a way that our trainees have a clear understanding about developing layouts from schematics following the design constraints, process challenges and layout guidelines and verified their designs and extracted within the given specification limits.

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